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CY28312B-2 Datasheet, PDF (14/17 Pages) SpectraLinear Inc – FTG for VIA™ K7 Series Chipset with Programmable Output Frequency
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CY28312B-2
DC Electrical Characteristics TA = 0°C to +70°C, VDD = 3.3V ± 5% and 2.5V ± 5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
COUT
LIN
Output Pin Capacitance
Input Pin Inductance
6
pF
7
nH
AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, fXTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated
operating conditions using the stated lump capacitive load at
the clock output; Spread Spectrum is disabled.
CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)[6]
Parameter
Description
Test Condition/Comments
tR
Output Rise Edge Rate CPU_CS
tF
Output Fall Edge Rate CPU_CS
tD
Duty Cycle
Measured at 50% point
tJC
Jitter, Cycle to Cycle
fST
Frequency Stabilization Assumes full supply voltage reached
from Power-up (cold within 1 ms from power-up. Short
start)
cycles exist prior to frequency
stabilization.
Zo
AC Output Impedance VO = VX
CPU = 100 MHz
Min. Typ. Max.
1.0
4.0
1.0
4.0
45
55
250
3
50
CPU = 133 MHz
Min. Typ. Max. Unit
1.0
4.0 V/ns
1.0
4.0 V/ns
45
55 %
250 ps
3
ms
50
W
PCI Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
tP
Period
Measured on rising edge at 1.5V
30
tH
High Time
Duration of clock cycle above 2.4V
12
tL
Low Time
Duration of clock cycle below 0.4V
12
tR
Output Rise Edge Rate Measured from 0.8V to 2.0V
1
tF
Output Fall Edge Rate Measured from 2.0V to 0.8V
1
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum difference
of cycle time between two adjacent cycles.
tSK
Output Skew
Measured on rising edge at 1.5V
tO
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge 1.5
at 1.5V. CPU leads PCI output.
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold start) power-up. Short cycles exist prior to frequency stabilization.
Zo
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
Typ.
30
Max.
4
4
55
250
500
4
3
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
:
AGP Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
tR
Output Rise Edge Rate Measured from 0.8V to 2.0V
tF
Output Fall Edge Rate Measured from 2.0V to 0.8V
tD
Duty Cycle
Measured at 1.5V
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum difference
of cycle time between two adjacent cycles.
Note:
6. Refer to Figure 1 for K7 operation clock driver test circuit.
Min.
0.5
0.5
45
Typ.
Max.
2.0
2.0
55
250
Unit
V/ns
V/ns
%
ps
Rev 1.0, November 21, 2006
Page 14 of 17
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