CY28312B-2 Datasheet, PDF (2/17 Pages) SpectraLinear Inc – FTG for VIA™ K7 Series Chipset with Programmable Output Frequency

CY28312B-2
Pin Definitions
Pin Name
REF0/FS0
REF1/FS1
REF2
X1
X2
PCI_F/FS4
PCI_0/SEL24_48#
PCI1:8
PCI9_E
AGP0:2
48MHz/FS2
24_48MHz/FS3
RST#
CPUT0, CPUC0
CPUT_CS,
CPUC_CS
CPU_STOP#
PCI_STOP#
AGP_STOP#
REF_STOP#
PD#
Pin No.
48
47
46
3
4
9
10
11, 13, 14, 16,
17, 18, 20, 21
22
26, 27, 28
6
7
24
42, 41
39, 38
36
35
44
45
34
Pin
Type
Pin Description
I/O Reference Clock Output 0/Frequency Select 0. 3.3V 14.318-MHz clock
output. REF0 will be disabled when REF_STOP# is active. This pin also serves
as the select strap to determines device operating frequency as described in
Table 4.
I/O Reference Clock Output 0/Frequency Select 1. 3.3V 14.318-MHz clock
output. REF1 will be disabled when REF_STOP# is active. This pin also serves
as the select strap to determines device operating frequency as described in
Table 4.
I/O Reference Clock Output 2. 3.3V 14.318-MHz clock output. REF2 will be
disabled when REF_STOP# is active.
I Crystal Input. This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
I Crystal Output. An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left unconnected.
I Free-Running PCI Clock/Frequency Select 4. 3.3V 33-MHz free running PCI
clock output. This pin also serves as the select strap to determines device
operating frequency as described in Table 4.
I/O PCI Clock 0/Select 24 or 48 MHz. 3.3V 33-MHz PCI clock outputs. This output
will be disabled when PCI_STOP# is active. This pin also serves as the select
strap to determine device operating frequency of 24_48MHz output.
O PCI Clock 1 through 8. 3.3V 33-MHz PCI clock outputs. PCI1:8 will be disabled
when PCI_STOP# is active.
O Early PCI Clock 9. 3.3V 33-MHz PCI clock outputs. PCI9_E will be disabled
when PCI_STOP# is active.
O AGP Clock 0 through 2. 3.3V 66-MHz clock outputs. The operating frequency
is controlled by FS0:4 (see Table 4). AGP0:2 will be disabled when
AGP_STOP# is active.
I/O 48-MHz Output/Frequency Selection 3. 3.3V 48-MHz non-spread spectrum
output. 48 MHz will be disabled when REF_STOP# is active. This pin also
serves as the select strap to determine device operating frequency as described
in Table 4.
I/O 24- or 48-MHz Output/Select 24 or 48 MHz. 3.3V 24 or 48-MHz non-spread
spectrum output. 24_48MHz will be disabled when REF_STOP# is active. This
pin also serves as the select strap to determine device operating frequency as
described in Table 4.
O Reset#. Open-drain RESET# output.
(open-
drain)
O CPU Clock Output 0. CPUT0 and CPUC0 are the differential CPU clock
(open- outputs for the K7 processor. They are open-drain outputs.
drain)
O CPU Clock Output for Chipset. CPUT_CS and CPUC_CS are the differential
CPU clock outputs for the chipset. They are push-pull outputs. These outputs
will be disabled when CPU_STOP# is active.
I CPU STOP Input. This input will disable CPUT_CS and CPUC_CS when it is
active.
I PCI STOP Input. This input will disable PCI0:8 and PCI9_E when it is active.
I AGP STOP Input. This input will disable AGP0:2 when it is active.
I REF STOP Input. This input will disable REF0:2, 24_48MHz and 48 MHz
outputs when it is active.
I Power-down Input. This input will trigger the clock generator into Power-down
mode when it is active.
Rev 1.0, November 21, 2006
Page 2 of 17