W209C Datasheet, PDF (8/15 Pages) SpectraLinear Inc – Frequency Generator for Integrated Core Logic with 133MHz FSB

W209C
Byte 3: Reserved Register (1 = Enable, 0 = Disable)
Bit
Bit 7
Pin#
31
Name
DCLK
Bit 6
Bit 5
Bit 4
-
Reserved
-
Reserved
-
Reserved
Bit 3
Bit 2
Bit 1
47
APIC
-
Reserved
-
Reserved
Bit 0
-
Reserved
Default
1
0
0
0
1
0
1
0
(Active/Inactive)
Reserved
Reserved
Reserved
(Active/Inactive)
Reserved
Reserved
Reserved
Pin Description
Byte 4: Reserved Register (1 = Enable, 0 = Disable)
Bit
Bit 7
Pin#
-
Name
SEL3
Default
0
See Table 4
Pin Function
Bit 6
Bit 5
Bit 4
-
SEL2
-
SEL1
-
SEL0
0
See Table 4
0
See Table 4
0
See Table 4
Bit 3
Bit 2
-
FS(0:4) Override
-
SEL4
0
0 = Select operating frequency by FS(0:4) strapping
1 = Select operating frequency by SEL(0:4) bit settings
0
See Table 4
Bit 1
Bit 0
-
Reserved
-
Test Mode
1
Reserved
0
0 = Normal
1 = Three-stated
Byte 5: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Bit 7
Bit 6
Bit 5
-
Reserved
-
Reserved
-
Reserved
Bit 4
Bit 3
Bit 2
-
Reserved
-
Reserved
-
Reserved
Bit 1
Bit 0
-
Reserved
-
Reserved
Default
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin Description
Byte 6: Reserved Register (1 = Enable, 0 = Disable)
Bit
Bit 7
Pin#
-
Name
Reserved
Bit 6
Bit 5
Bit 4
-
Reserved
-
Reserved
-
Reserved
Bit 3
Bit 2
Bit 1
-
Reserved
-
Reserved
-
Reserved
Default
0
0
0
0
0
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin Description
Rev 1.0, November 20, 2006
Page 8 of 15