W209C Datasheet, PDF (13/15 Pages) SpectraLinear Inc – Frequency Generator for Integrated Core Logic with 133MHz FSB

W209C
Group Skew and Jitter Limits
Output Group
CPU
SDRAM
APIC
48MHz
3V66
PCI
REF
Pin-Pin Skew Max.
175 ps
250 ps
250 ps
250 ps
175 ps
500 ps
N/A
Cycle-Cycle Jitter
250 ps
250 ps
500 ps
500 ps
500 ps
500 ps
1000 ps
Duty Cycle
45/55
45/55
45/55
45/55
45/55
45/55
45/55
Nom Vdd
2.5V
3.3V
2.5V
3.3V
3.3V
3.3V
3.3V
Skew, Jitter
Measure
Point
1.25V
1.5V
1.25V
1.5V
1.5V
1.5V
1.5V
Typical Output
Impedance
21 :
14 :
16 :
21 :
14 :
14 :
11 :
Output
Buffer
Test Point
Clock Output Wave
2.0
1.25
2.5V Clocking
Interface
0.4
T_HIGH
Test Load
T_PERIOD
Duty Cycle
T_RISE
T_FALL
T_LOW
T_HIGH
T_PERIOD
Duty Cycle
2.4
3.3V Clocking ^1.5
Interface ^0.4
T_RISE
T_FALL
T_LOW
Figure 8. Output Buffer
Layout Diagram
Rev 1.0, November 20, 2006
Page 13 of 15