W209C Datasheet, PDF (7/15 Pages) SpectraLinear Inc – Frequency Generator for Integrated Core Logic with 133MHz FSB

W209C
W209C Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register (1 = Enable, 0 = Disable)^[8]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
-
-
23
21, 22
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
24/48 MHz
48 MHz
Reserved
2. All unused register bits (reserved and N/A) should be
written to a “0” level.
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in
higher than normal operating current. The controller will
read back the written value.
Default
0
0
0
0
0
1
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
(Active/Inactive)
(Active/Inactive)
Reserved
Pin Function
Byte 1: Control Register (1 = Enable, 0 = Disable)^[8]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
32
33
35
36
37
39
40
41
Name
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Default
1
1
1
1
1
1
1
1
Pin Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 2: Control Register (1 = Enable, 0 = Disable)^[8]
Bit
Pin#
Name
Default
Pin Description
Bit 7
19
PCI7
1
(Active/Inactive)
Bit 6
18
PCI6
1
(Active/Inactive)
Bit 5
17
PCI5
1
(Active/Inactive)
Bit 4
15
PCI4
1
(Active/Inactive)
Bit 3
14
PCI3
1
(Active/Inactive)
Bit 2
12
PCI2
1
(Active/Inactive)
Bit 1
11
PCI1
1
(Active/Inactive)
Bit 0
10
PCI0
1
(Active/Inactive)
Note:
8. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Rev 1.0, November 20, 2006
Page 7 of 15