W40S11-02 Datasheet, PDF (7/9 Pages) Cypress Semiconductor – SDRAM Buffer - 2 DIMM (Mobile)

W40S11-02
DC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 3.3V±5%
Parameter
Description
Test Condition/Comments
Min
Typ
I_DD
3.3V Supply Current
at 66 MHz
120
I_DD
3.3V Supply Current
at 100 MHz
185
I_{DD Tristate}
3.3V Supply Current in
5
Three-State
Logic Inputs
V_IL
Input Low Voltage
V_IH
Input High Voltage
I_ILEAK
Input Leakage Current, BUF_IN
I_ILEAK
Input Leakage Current^[3]
Logic Outputs (SDRAM0:9)^[4]
V_SS – 0.3
2.0
–5
–20
V_OL
Output Low Voltage
V_OH
Output High Voltage
I_OL
Output Low Current
I_OH
Output High Current
Pin Capacitance/Inductance
I_OL = 1 mA
I_OH = –1 mA
V_OL = 1.5V
V_OH = 1.5V
3.1
70
110
65
100
C_IN
Input Pin Capacitance
C_OUT
Output Pin Capacitance
L_IN
Input Pin Inductance
Note:
3. OE, SDATA, and SCLOCK logic pins have a 250-k: internal pull-up resistor (V_DD – 0.8V).
4. All SDRAM outputs loaded by 6" transmission lines with 22-pF capacitors on ends.
Max
Unit
160
mA
220
mA
10
mA
0.8
V
V_DD + 0.5
V
+5
µA
+5
µA
50
mV
V
185
mA
160
mA
5
pF
6
pF
7
nH
AC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 3.3V±5% (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition
Min
Typ
Max
f_IN
Input Frequency
0
133
t_R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1.5
4.0
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1.5
4.0
t_SR
Output Skew, Rising Edges
250
t_SF
Output Skew, Falling Edges
250
t_EN
Output Enable Time
1.0
8.0
t_DIS
Output Disable Time
1.0
8.0
t_PR
Rising Edge Propagation Delay
1.0
5.0
t_PF
Falling Edge Propagation Delay
1.0
5.0
t_D
Duty Cycle
Measured at 1.5V
45
55
Z_o
AC Output Impedance
15
Unit
MHz
V/ns
V/ns
ps
ps
ns
ns
ns
ns
%
:
Rev 1.0, Dec. 01, 2006
Page 7 of 9