W40S11-02 Datasheet, PDF (2/9 Pages) Cypress Semiconductor – SDRAM Buffer - 2 DIMM (Mobile)

W40S11-02
Pin Definitions
Pin Name
SDRAM0:9
BUF_IN
SDATA
SCLOCK
VDD
GND
OE
Pin
No.
2, 3, 6, 7,
22, 23, 26,
27, 11, 18
9
14
15
1, 5, 10, 13,
19, 24, 28
4, 8, 12, 16,
17, 21, 25
20
Pin
Type
O
I
I/O
I
P
G
Pin Description
SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a
rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled
to within ±250 ps of each other.
Clock Input: This clock input has an input threshold voltage of 1.5V (typ).
SMBus Data Input: Data should be presented to this input as described in the SMBus
section of this data sheet. Internal 250-k: pull-up resistor.
SMBus Clock Input: The SMBus Data clock should be presented to this input as
described in the SMBus section of this data sheet. Internal 250-k: pull-up resistor.
Power Connection: Power supply for core logic and output buffers. Connected to
3.3V supply.
Ground Connection: Connect all ground pins to the common system ground plane.
I
Output Enable: Internal 250-k: pull-up resistor. Three-states outputs when LOW.
Functional Description
Output Control Pins
Outputs three-stated when OE = 0, and toggle when OE = 1.
Outputs are in phase with BUF_IN but are phase delayed by
1 to 5 ns. Outputs can also be controlled via the SMBus
interface.
Table 1. Byte Writing Sequence
Output Drivers
The W40S11-02 output buffers are CMOS type which deliver
a rail-to-rail (GND to V_DD) output voltage swing into a nominal
capacitive load. Thus, output signaling is both TTL and CMOS
level compatible. Nominal output buffer impedance is 15
ohms.
Operation
Data is written to the W40S11-02 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 1.
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address 11010010
Commands the W40S11-02 to accept the bits in Data Bytes 0–6 for
internal register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W40S11-02
is 11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
Command
“Don’t Care”
Unused by the W40S11-02, therefore bit values are ignored (“Don’t
Code
Care”). This byte must be included in the data write sequence to maintain
proper byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
3
Byte Count
“Don’t Care”
Unused by the W40S11-02, therefore bit values are ignored (“Don’t
Care”). This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standard serial
communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
4
Data Byte 0
Refer to Table 2 The data bits in these bytes set internal W40S11-23 registers that control
5
Data Byte 1
device operation. The data bits are only accepted when the Address Byte
bit sequence is 11010010, as noted above. For description of bit control
6
Data Byte 2
functions, refer to Table 2, Data Byte Serial Configuration Map.
7
Data Byte 3
Don’t Care
Refer to Cypress clock drivers.
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
Rev 1.0, Dec. 01, 2006
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