W144 Datasheet, PDF (5/13 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

W144
Serial Data Interface
The W144 features a two-pin, serial data interface that can be
used to configure internal register settings that control
particular device functions. Upon power-up, the W144
initializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic
outputs of the chipset. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
power management functions. Table 3 summarizes the control
functions of the serial data interface.
Operation
Data is written to the W144 in eleven bytes of eight bits each.
Bytes are written in the order shown in Table 4.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Clock Output Disable
Description
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
Spread Spectrum
Enabling
Output Three-state
(Reserved)
Enables or disables spread spectrum clocking.
Puts clock output into a high-impedance state.
Reserved function for future device revision or
production device testing.
Common Application
Unused outputs are disabled to reduce EMI
and system power. Examples are clock outputs
to unused PCI slots.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change under
normal system operation.
For EMI reduction.
Production PCB testing.
No user application. Register bit must be
written as 0.
Table 4. Byte Writing Sequence
Byte
Sequence
Byte Name
1
Slave Address
Bit Sequence
11010010
2
Command Code Don’t Care
3
Byte Count
Don’t Care
Byte Description
Commands the W144 to accept the bits in Data Bytes 0–6 for internal
register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W144 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W144, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
Unused by the W144, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
Rev 1.0, November 21, 2006
Page 5 of 13