W144 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

W144
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
• Maximized electromagnetic interference (EMI)
suppression using Cypress’ Spread Spectrum
technology
• Single chip system frequency synthesizer for Intel^®
440BX AGPset
• Two copies of CPU output
• Six copies of PCI output 1
• One 48 MHz output for USB
• One 24 MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for three
DIMMs
• Supports frequencies up to 150 MHz
• I²C interface for programming
• Power management control inputs
Logic Block Diagram
X1
XTAL
X2
OSC
PLL Ref Freq
I/O Pin
Control
Stop
Clock
Control
CLK_STOP#
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
SDRAMIN
I²C
Logic
Stop
Clock
Control
PLL2
÷2
Stop
Clock
Control
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC
VDDQ2
CPU1
CPU_F
VDDQ3
PCI_F/MODE
PCI1/FS3
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS0
24MHz/FS1
VDDQ3
SDRAM0:11
12
SDRAM_F
Table 1. Pin Selectable Frequency
Input Address
FS3 FS2 FS1 FS0
11 11
11 10
11 01
11 00
10 11
10 10
10 01
10 00
01 11
01 10
01 01
01 00
00 11
00 10
00 01
00 00
CPU_F, CPU1
(MHz)
133.6
124
150
140
105
110
115
120
100.2
133.3
112
103
66.8
83.3
75
124
PCI_F, 1:5 (MHz)
33.4 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
33.4 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
Pin Configuration^[1]
VDDQ3 1
REF0/(PCI_STOP#) 2
GND 3
X1 4
X2 5
VDDQ3 6
PCI_F/MODE 7
**PCI1/FS3 8
GND 9
PCI2 10
PCI3 11
PCI4 12
PCI5 13
VDDQ3 14
SDRAMIN 15
GND 16
SDRAM11 17
SDRAM10 18
VDDQ3 19
SDRAM9 20
SDRAM8 21
{ ^GND
I²C ^SDATA
22
23
SCLK 24
48 VDDQ2
47 IOAPIC
46 REF1/FS2*
45 GND
44 CPU_F
43 CPU1
42 VDDQ2
41 CLK_STOP#
40 SDRAM_F
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS0*
25 24MHz/FS1*
Note:
1. * Has an internal pull-up resistors. It should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping
while ** has an internal pull down resistor.
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
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