W144 Datasheet, PDF (10/13 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

W144
DC Electrical Characteristics T_A = 0°C to +70°C; V_DDQ3 = 3.3V±5%; V_DDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max. Unit
Crystal Oscillator
V_TH
X1 Input threshold Voltage^[6]
C_LOAD
Load Capacitance, Imposed on
External Crystal^[7]
C_IN,X1
X1 Input Capacitance^[8]
Pin Capacitance/Inductance
V_DDQ3 = 3.3V
Pin X2 unconnected
–
1.65
–
14
–
28
–
V
–
pF
–
pF
C_IN
C_OUT
L_IN
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
Except X1 and X2
–
–
–
–
–
–
5
pF
6
pF
7
nH
AC Electrical Characteristics
T_A = 0°C to +70°C; V_DDQ3 = 3.3V±5%; V_DDQ2 = 2.5V±5%;
f_XTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated
operating conditions using the stated lump capacitive load at
the clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU_F, CPU1 (Lump Capacitance Test Load = 20 pF)
CPU = 66.6 MHz CPU = 100.2 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.25
15 – 15.5 9.98 – 10.5 ns
t_H
High Time
Duration of clock cycle above 2.0V
5.6 –
– 3.3 –
– ns
t_L
Low Time
Duration of clock cycle below 0.4V
5.3 –
– 3.1 –
– ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1.5 –
4 1.5 –
4 V/ns
t_F
Output Fall Edge Rate Measured from 2.0V to 0.4V
1.5 –
4 1.5 –
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45 – 55 45 – 55 %
1.25V
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V.
– – 200 – – 200 ps
Maximum difference of cycle time
between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.25V
– – 250
250 ps
f_ST
Frequency Stabilization Assumes full supply voltage reached
–
–
3
––
3 ms
from Power-up (cold within 1 ms from power-up. Short cycles
start)
exist prior to frequency stabilization.
Z_o
AC Output Impedance Average value during switching
– 20 – – 20 – :
transition. Used for determining series
termination value.
Notes:
6. X1 input threshold voltage (typical) is V_DDQ3/2.
7. The W144 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;
this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Rev 1.0, November 21, 2006
Page 10 of 13