CY28437 Datasheet, PDF (1/22 Pages) SpectraLinear Inc – Clock Generator for Intel Grantsdale Chipset

PRELIMINARY
CY28437
Clock Generator for Intel^£Grantsdale Chipset
Features
• Compliant to Intel^£ CK410
• Supports Intel Prescott and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
• 33 MHz PCI clock
• Dynamic Frequency Control
Block Diagram
Xin
14.318MHz
Xout
Crystal
PLL Reference
FS_[E:A]
CPU
PLL
Divider
VTTPWR_GD#/PD
DF_EN
DF[2:0]
SDATA
SCLK
SRC
PLL
Divider
SATA
PLL
Divider
FIX
PLL
Divider
Dynamic
Frequency
I2C
Logic
Watchdog
Timer
• Dial-A-Frequency^£
• Watchdog timer
• Two Independent Overclocking PLLs
• Low-voltage frequency select input
• I²C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
CPU SRC
PCI
REF DOT96 USB
x2
x8
x8
x2
x1
x2
VDD_RE
F
RE
F
IREF
VDD_CPU
CPUT
CPUC
VDD_SRC
SRCT
SRCC
VDD_SRC
SRCT4_SATA
SRCC4_SATA
VDD_48Mhz
DOT96T
DOT96C
VDD_48
USB48
VDD_PCI
PCI
VDD_PCI
PCIF
Pin Configuration
VDD_PCI
1
56
VSS_PCI
2
55
DF2/PCI3
3
54
*FS_E/PCI4
4
53
PCI5
5
52
VSS_PCI
6
51
VDD_PCI
7
50
**DF_EN/PCIF0
8
49
**SRESET_EN/PCIF1
9
48
VTT_PWRGD#/PD
10
47
VDD_48
11
46
**FS_A/USB48_0
12
45
VSS_48
13
44
DOT96T
14
43
DOT96C
15
42
*FS_B/USB48_1
16
41
SRCT0
17
40
SRCC0
18
39
SRCT1
19
38
SRCC1
20
37
VDD_SRC
21
36
SRCT2
22
35
SRCC2
23
34
SRCT3
24
33
SRCC3
25
32
SRCT4_SATA
26
31
SRCC4_SATA
27
30
VDD_SRC
28
29
* Indicates internal pull-up
** Indicates internal pull-down
PCI2/DF1
PCI1/DF0
PCI0/SRESET#
REF1/**FS_C
REF0/**FS_D
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
SRCT7
SRCC7
VDD_SRC
SRCT6
SRCC6
SRCT5
SRCC5
VSS_SRC
SRESET#
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
Page 1 of 22
www.SpectraLinear.com