S70WS512N00 Datasheet, PDF (87/93 Pages) SPANSION – Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory

Advance Information
13.1
Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and back-ward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address (BA)555h any time the device is ready to read array data. The system can read CFI in-
formation at the addresses given in Tables 13.3–13.6) within that bank. All reads outside of the
CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed,
writes are not. To terminate reading CFI data, the system must write the reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0098; /* write CFI entry command
*/
/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0; /* write cfi exit command
*/
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A
and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these
documents.
Addresses
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
Table 13.3 CFI Query Identification String
Data
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Description
Query Unique ASCII string QRY
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
Addresses
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
Data
0017h
0019h
0000h
0000h
0006h
0009h
000Ah
0000h
0004h
0004h
0003h
0000h
Table 13.4 System Interface String
Description
V_CC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
V_CC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
V_PP Min. voltage (00h = no V_PP pin present)
V_PP Max. voltage (00h = no V_PP pin present)
Typical timeout per single byte/word write 2^N µs
Typical timeout for Min. size buffer write 2^N µs (00h = not supported)
Typical timeout per individual block erase 2^N ms
Typical timeout for full chip erase 2^N ms (00h = not supported)
Max. timeout for byte/word write 2^N times typical
Max. timeout for buffer write 2^N times typical
Max. timeout per individual block erase 2^N times typical
Max. timeout for full chip erase 2^N times typical (00h = not supported)
88
S70WS512N00 Based MCPs
S70WS512N00_00_A0 March 14, 2005