S29CD-J Datasheet, PDF (44/76 Pages) SPANSION – 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O

Data Sheet (Preliminary)
locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either
putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to
reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device
operates normally again.
Table 9.1 Sector Protection Schemes
DYB
0
0
0
1
1
0
1
1
PPB
0
0
1
0
1
1
0
1
PPB Lock
0
1
0
0
0
1
1
1
Sector State
Unprotected—PPB and DYB are changeable
Unprotected—PPB not changeable, DYB is changeable
Protected—PPB and DYB are changeable
Protected—PPB not changeable, DYB is changeable
9.5
Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector Protection
Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition to this password
requirement, after power-up and reset, the PPB Lock Bit is set “1” in order to maintain the password mode of
operation. Successful execution of the Password Unlock command by entering the entire password clears the
PPB Lock Bit, allowing for sector PPBs modifications.
Notes
1. There is no special addressing order required for programming the password. Once the password
is written and verified, the Password Mode Locking Bit must be set in order to prevent access.
2. The Password Program Command is only capable of programming “0”s. Programming a “1” after a
cell is programmed as a “0” results in a time-out with the cell as a “0”. (This is an OTP area).
3. The password is all “1”s when shipped from the factory.
4. When the password is undergoing programming, Simultaneous Read/Write operation is disabled.
Read operations to any memory location returns the programming status. Once programming is
complete, the user must issue a Read/Reset command to return the device to normal operation.
5. All 64-bit password combinations are valid as a password.
6. There is no means to read, program or erase the password is after it is set.
7. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and
further password programming.
8. The Password Mode Lock Bit is not erasable.
9. The exact password must be entered in order for the unlocking function to occur.
10. There is a built-in 2-µs delay for each password check. This delay is intended to stop any efforts to
run a program that tries all possible combinations in order to crack the password.
9.6 Hardware Data Protection Methods
The device offers several methods of data protection by which intended or accidental erasure of any sectors
can be prevented via hardware means. The following subsections describe these methods.
9.6.1
WP# Method
The Write Protect feature provides a hardware method of protecting the two outermost sectors of the large
bank.
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S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September 27, 2006