S29JL032H_09 Datasheet, PDF (42/61 Pages) SPANSION – 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory

Data Sheet
11.7
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also applies after each additional sector erase command. When
the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase
commands from the system can be assumed to be less than 80 µs, the system need not monitor DQ3. See
also Sector Erase Command Sequence on page 34.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands.
To ensure the command has been accepted, the system software should check the status of DQ3 prior to and
following each subsequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted.
Table 11.1 shows the status of DQ3 relative to the other status bits.
Table 11.1 Write Operation Status
Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
Standard
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
N/A
No toggle
0
0
1
Toggle
0
Erase
Erase-Suspend-
Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Suspend
Mode
Read
Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
Notes
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the
section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in
progress. The device outputs array data if the system addresses a non-busy bank.
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S29JL032H
S29JL032H_00_B8 August 31, 2009