S29JL032H_09 Datasheet, PDF (15/61 Pages) SPANSION – 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory

Data Sheet
8.4
8.5
8.6
8.7
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while programming or erasing in the other
bank of memory. An erase operation may also be suspended to read from or program to another location
within the same bank (except the sector being erased). Figure 17.8 on page 52 shows how read and write
cycles may be initiated for simultaneous operation with zero latency. I_CC6 and I_CC7 in DC Characteristics
on page 44 represent the current specifications for read-while-program and read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V_CC ± 0.3 V.
(Note that this is a more restricted voltage range than V_IH.) If CE# and RESET# are held at V_IH, but not within
V_CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device
requires standard access time (t_CE) for read access when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
I_CC3 in DC Characteristics on page 44 represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t_ACC + 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. I_CC5 in DC
Characteristics on page 44 represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of t_RP, the device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V_SS±0.3 V, the device
draws CMOS standby current (I_CC4). If RESET# is held at V_IL but not within V_SS±0.3 V, the standby current
will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a time of t_READY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is
completed within a time of t_READY (not during Embedded Algorithms). The system can read data t_RH after the
RESET# pin returns to V_IH.
Refer to AC Characteristics on page 47 for RESET# parameters and to Figure 17.2 on page 48 for the timing
diagram.
August 31, 2009 S29JL032H_00_B8
S29JL032H
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