S25FL128P_12 Datasheet, PDF (37/49 Pages) SPANSION – 128 Megabit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Bus

Data Sheet
CS#
SCK
SI
Hi-Z
SO
Figure 11.20 Serial Release from Deep Power Down and
Read Electronic Signature (RES) Command Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
Command
3 Dummy Bytes
t_RES
23 22 21
MSB
32 1 0
7 654 32 10
MSB
Electronic ID out
Deep Power-down Mode
Standby Mode
11.14.2
Parallel Mode
When the device is in parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a
single clock cycle instead of eight clock cycles to access the next data byte. The method of memory content
output will be the same compared to outside of parallel mode. The only difference is that a byte of data is
output per clock cycle instead of a single bit. In this case, the Electronic Signature will be output onto the
P0[7–0] parallel output pins.
Figure 11.21 Parallel Release from Deep Power Down and
Read Electronic Signature (RES) Command Sequence
CS#
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
Command
3 Dummy Bytes
t_RES
SI
Hi-Z
PO[7-0]
23 22 21
MSB
32 1 0
Electronic ID
Byte
1
Deep Power-down Mode
Standby Mode
Notes
1. In parallel mode, the maximum access clock frequency (Fsck) is 10 MHz (SCK pin clock frequency).
2. To release the device from Deep Power Down and read Electronic ID in parallel mode, a Parallel Mode Enter command (55h) must be issued before the RES
command. The device will not exit parallel mode until a Parallel Mode Exit command (45h) is written, or upon power-down or power-up sequence.
3. Byte 1 will output the Electronic Signature.
September 21, 2012 S25FL128P_00_11
S25FL128P
37