S25FL128P_12 Datasheet, PDF (23/49 Pages) SPANSION – 128 Megabit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Bus

Data Sheet
11.3.2
Parallel Mode
In parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a single clock cycle
instead of eight clock cycles to access the next data byte. The method of memory content output will be the
same compared to the serial mode. The only difference is that a byte of data is output per clock cycle instead
of a single bit. In this case, the manufacturer identification will be output during the first byte cycle and the
device identification during the second and third byte cycles out of the PO7-PO0 serial output pins. To read ID
in parallel mode requires a Parallel Mode Entry command (55h) to be issued before the RDID command.
Once in the parallel mode, the flash memory will not exit parallel mode until a Parallel Mode Exit (45h)
command is given to the flash device, or upon power down/power up sequence.
Figure 11.5 Parallel Read_ID Command Sequence and Data Out Sequence
CS#
SCK
SI
PO[7-0]
0 1 2 3 4 5 6 7 8 9 10 11 12
Instruction
High Impedance
Manufacturer/Device Identification
Byte Byte Byte Byte Byte
0
1
2
3
4
Device
Uniform 256 KB Sector
Uniform 64 KB Sector
Table 11.1 Manufacturer & Device Identification, RDID (9Fh)
Manufacturer Identification
Byte 0
01h
01h
Device Identification
Byte 1
Byte 2
20h
18h
20h
18h
Extended Device Identification
Byte 3
Byte 4
03h
00h
03h
01h
September 21, 2012 S25FL128P_00_11
S25FL128P
23