S25FL032P0XMFI000 Datasheet, PDF (37/69 Pages) SPANSION – 32-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

Data Sheet
9.11
Read Status Register (RDSR)
The Read Status Register (RDSR) command outputs the state of the Status Register bits. Table 9.8 shows
the status register bits and their functions. The RDSR command may be written at any time, even while a
program, erase, or Write Registers operation is in progress. The host system should check the Write In
Progress (WIP) bit before sending a new command to the device if an operation is already in progress.
Figure 9.13 shows the RDSR command sequence, which also shows that it is possible to read the Status
Register continuously until CS# is driven high. The maximum clock frequency for the RDSR command is
104 MHz.
Table 9.8 S25FL032P Status Register
Bit
Status Register Bit
Bit Function
Description
1 = Protects when W#/ACC is low
7
SRWD
Status Register Write Disable
0 = No protection, even when W#/ACC is low
0 = No Error
6
P_ERR
Programming Error Occurred
1 = Error occurred
5
E_ERR
Erase Error Occurred
0 = No Error
1 = Error occurred
4
BP2
3
BP1
Block Protect
Protects selected Block from Program or Erase
2
BP0
1
WEL
Write Enable Latch
1 = Device accepts Write Registers, program or erase commands
0 = Ignores Write Registers, program or erase commands
0
WIP
Write in Progress
1 = Device Busy a Write Registers, program or erase operation is in
progress
0 = Ready. Device is in standby mode and can accept commands.
Figure 9.13 Read Status Register (RDSR) Command Sequence
CS#
Mode 3
SCK _{Mode 0}
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
SO ^Hi-Z
7654 3 2 107 654 32 107
MSB _{Status Register Out}
MSB _{Status Register Out}
The following describes the status and control bits of the Status Register.
Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Registers, program, or
erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of these
operations is in progress; if WIP is 0, no such operation is in progress. This bit is a Read-only bit.
Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Registers,
program, or erase command. When set to 1, the device accepts these commands; when set to 0, the device
rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the WRDI
command, and is also automatically reset to 0 after the completion of a Write Registers, program, or erase
operation, and after a power down/power up sequence. WEL cannot be directly set by the WRR command.
January 29, 2013 S25FL032P_00_09
S25FL032P
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