S25FL032P0XMFI000 Datasheet, PDF (27/69 Pages) SPANSION – 32-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

Data Sheet
9.4
Quad Output Read Mode (QOR)
The Quad Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out
4 bits at a time using 4 pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3) instead of 1 bit, at a maximum
frequency of 80 MHz. The Quad Output Read mode effectively doubles the data transfer rate compared to the
Dual Output Read instruction, and is four times the data transfer rate of the FAST_READ instruction.
The host system must first select the device by driving CS# low. The Quad Output Read command is then
written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge
of SCK. Then the memory contents, at the address that are given, are shifted out four bits at a time through
IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#) pins at a frequency f_C on the falling edge of SCK.
The Quad Output Read command sequence is shown in Figure 9.4 and Table 9.1 on page 23. The first
address byte specified can start at any location of the memory array. The device automatically increments to
the next higher address after each byte of data is output. The entire memory array can therefore be read with
a single Quad Output Read command. When the highest address is reached, the address counter reverts to
00000h, allowing the read sequence to continue indefinitely.
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.
The Quad Output Read command is terminated by driving CS# high at any time during data output. The
device rejects any Quad Output Read command issued while it is executing a program, erase, or Write
Registers operation, and continues the operation uninterrupted.
The Quad bit of Configuration Register must be set (CR Bit1 = 1) to enable the Quad mode capability of the
S25FL device.
CS#
SCK
SI/IO0
SO/IO1
W#/ACC/IO2
HOLD#/IO3
Figure 9.4 Quad Output Read Instruction Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Instruction
Hi-Z
Hi-Z
Hi-Z
24 Bit
Address
Dummy Byte
SI Switches from Input to Output
23 22 21
*
321 0 765 43 210 _{40 40} 40 40 ₄
*
5 15 1 5 1 5 1 5
62626262 6
7 3 7 37 3 7 37
*
*
*
*
*
DATA DATA DATA DATA
OUT 1 OUT 2 OUT 3 OUT 4
*MSB
January 29, 2013 S25FL032P_00_09
S25FL032P
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