S25FL128SAGMFI001 Datasheet, PDF (124/153 Pages) SPANSION – CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

CS#
SCK
SI
Data Sheet
Figure 10.73 DYBWR Command Sequence
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
Instruction
32-Bit
Address
Data Byte 1
7 6 5 4 3 2 1 0 31 30 29
MSB
3 2 1 0 7 6 5 4 3 210
MSB
10.8.5
PPB Read (PPBRD E2h)
The instruction E2h is shifted into SI by the rising edges of the SCK signal, followed by the 32-bit address
selecting location zero within the desired sector (note, the high order address bits not used by a particular
density device must be zero) Then the 8-bit PPB access register contents are shifted out on SO.
It is possible to read the same PPB access register continuously by providing multiples of eight clock cycles.
The address of the PPB register does not increment so this is not a means to read the entire PPB array. Each
location must be read with a separate PPB Read command. The maximum operating clock frequency for the
PPB Read command is 133 MHz.
Figure 10.74 PPBRD Command Sequence
CS#
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
Instruction
32-Bit
Address
7 6 5 4 3 2 1 0 31 30 29
High Impedance
321 0
DATA OUT 1
76543210
MSB
10.8.6
PPB Program (PPBP E3h)
Before the PPB Program (PPBP) command can be accepted by the device, a Write Enable (WREN)
command must be issued. After the Write Enable (WREN) command has been decoded, the device will set
the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The PPBP command is entered by driving CS# to the logic low state, followed by the instruction, followed by
the 32-bit address selecting location zero within the desired sector (note, the high order address bits not used
by a particular density device must be zero).
The PPBP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same
manner as any other programming operation.
CS# must be driven to the logic high state after the last bit of address has been latched in. If not, the PPBP
command is not executed. As soon as CS# is driven to the logic high state, the self-timed PPBP operation is
initiated. While the PPBP operation is in progress, the Status Register may be read to check the value of the
Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PPBP operation, and
is a 0 when it is completed. When the PPBP operation is completed, the Write Enable Latch (WEL) is set to a
0.
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S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012