S25FL128SAGMFI001 Datasheet, PDF (12/153 Pages) SPANSION – CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Data Sheet
2. Overview
2.1
General Description
The Spansion S25FL128S and S25FL256S devices are flash non-volatile memory products using:
 MirrorBit technology - that stores two data bits in each memory array transistor
 Eclipse architecture - that dramatically improves program and erase performance
 65 nm process lithography
This family of devices connect to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single
bit serial input and output (SIngle I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and
four bit (Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In
addition, the FL-S family adds support for Double Data Rate (DDR) read commands for SIO, DIO, and QIO
that transfer address and read data on both edges of the clock.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or
256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and
erase than prior generation SPI program or erase algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at
the higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can
match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal
count dramatically.
The S25FL128S and S25FL256S products offer high densities coupled with the flexibility and fast
performance required by a variety of embedded applications. They are ideal for code shadowing, XIP, and
data storage.
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S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012