S25FL128SAGMFI001 Datasheet, PDF (104/153 Pages) SPANSION – CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Data Sheet
Figure 10.43 DDR Fast Read Initial Access (4-byte Address, 0Eh or 0Dh [ExtAdd=1], EHPLC=01b)
CS#
SCLK
SI
SO
0
1
2
3
4
5
6
7
8
23
24
25
26
27
28
29
30
31
32
33
34
35
36
8 cycles
Instruction
16 cycles
32b Add
4 cycles
Mode
7
6
5
4
3
2
1
0
31 22 1 0 7 6 5 4 3 2 1 0
4 cycles Dummy
Optional DLP
4 cycles
per data
7 65432107654321076
Note:
1. Example DLP of 34h (or 00110100).
Figure 10.44 Continuous DDR Fast Read Subsequent Access
(4-byte Address [ExtAdd=1], EHPLC=01b)
CS#
SCLK
SI
0
16
17
18
19
20
21
22
8
23
24
25
26
27
28
16 cycles
32b Add
4 cycles
Mode
31 22 1 0 7 6 5 4 3 2 1 0
4 cycles Dummy
Optional DLP
4 cycles
per data
SO
Note:
1. Example DLP of 34h (or 00110100).
7 65432107654321076
Figure 10.45 DDR Fast Read Subsequent Access (4-byte Address, HPLC=01b)
CS#
0 1 2 3 4 5 6 7 8 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
8 cycles
16 cycles
6 cycles
4 cycles
Instruction
32b Add
Dummy
per data
SI
7 6 5 4 3 2 1 0 31 22 1 0
SO
7654321076
10.4.8
DDR Dual I/O Read (BDh, BEh)
The instruction
 BDh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 BDh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 BEh is followed by a 4-byte address (A31-A0)
104
S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012