C-13-2500-F-SLC Datasheet, PDF (3/8 Pages) Source Photonics, Inc. – 2.5Gbps Single Mode SFF LC Transceiver (SR)

Outline Drawing
2.5Gbps Single Mode SFF LC Transceiver (SR)
C-13-2500/C-F-SLC
Pinout Definitions
Pin
Symbol
1
RxGND
2
RxVcc
3
SD
4
RD-
5
RD+
6
TxVcc
7
TxGND
8
TxDIS
9
TD+
10
TD-
Attaching Posts
v
Notes
Directly connect this pin to the receiver ground plane
+3.3V dc power for the receiver section
Active high on this indicates a received optical signal (LVTTL or LVPECL)
Receiver Data out Bar(LVPECL/CML)
Receiver Data out (LVPECL/CML)
+3.3V dc power for the transmitter section
Directly connect this pin to the transmitter ground plane
Transmitter disable (LVTTL)
Transmitter Data In (LVPECL/CML)
Transmitter Data In Bar (LVPECL/CML)
The attaching posts are at the case potential and may be connected
chassis ground. They are not isolated from circuit ground.
Recommended Circuit Schematics
Inputs to the C-1x-2500/C-Fx-SLCx series transmitters are AC coupled and internally terminated through 50 ohm to AC ground. These
transceivers can operate with LVPECL or CML logic levels. The input signal must have at least a 200 mV peak to peak (single ended) signal
swing. Output from the receiver section of the module is also AC coupled and is expected to drive into 50 ohm load. Different termination
strategies may be required depending on the particular Serializer/Deserializer chip set used. The C-1x-2500/C-Fx-SLCx series product family
are designed with AC coupled data inputs and outputs to provide the following a advantages:
• Close positioning of SERDES with respect to transceiver; allow for shorter line lengths and at gigabit speeds reduces EMI.
• Mininum number of external components.
• Internal termination reduces the potential for unterminated stubs which would otherwise increase jitter and reduce
transmission margin.
Figure 1 & 2 illustrates the recommended transmit and receive data line terminations for SERDES with CML and LVPECL Inputs/outputs
respectively.