CXD3017Q Datasheet, PDF (94/117 Pages) Sony Corporation – CD Digital Signal Processor with Built-in Digital Servo and DAC

CXD3017Q
$39 (preset: $390000)
D15 D14 D13 D12 D11 D10 D9 D8
DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0
When $3A command SVDA = 0
DAC:
Serial data readout DAC mode setting.
When 0, serial data cannot be read out. (default)
When 1, serial data can be read out.
SD6 to SD0: These bits select the serial readout data.
D14 D13 D12 D11 D10 D9 D8
SD6 SD5 SD4 SD3 SD2 SD1 SD0
1
Coefficient RAM address
01
Data RAM address
0011111
0011110
0011101
0011100
0010100
0010011
0010010
0010001
0
0
0
1
1
∗
∗
0
0
0
1
0
∗
∗
0
0
0
0
1
∗
∗
0000011
0000010
0000001
0000000
Readout data
Coefficient RAM data
Data RAM data
RF AVRG register
RFDC input signal
FCS Bias register
TRVSC register
DFCT count
VC AVRG register
FE AVRG register
TE AVRG register
RFDC (Bottom)
RFDC (Peak)
RFDC (Peak – Bottom)
FE input signal
TE input signal
SE input signal
VC input signal
Note) When $3A SVDA is changed, select the readout data again.
Readout data
length
8 bits
16 bits
8 bits
8 bits
9 bits
9 bits
8 bits
8 bits
8 bits
8 bits
9 bits
9 bits
9 bits
8 bits
8 bits
8 bits
8 bits
∗: don't care
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