CXD3017Q Datasheet, PDF (42/117 Pages) Sony Corporation – CD Digital Signal Processor with Built-in Digital Servo and DAC

CXD3017Q
Signal
Description
PER0 to 7 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
FOK Focus OK
GFS High when the frame sync and the insertion protection timing match.
LOCK
GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight
consecutive samples, a low signal is output.
EMPH High when the playback disc has emphasis.
ALOCK
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is
output. If GFS is low eight consecutive samples, a low signal is output.
SPOA, B SPOA and B pin inputs.
WFCK Write frame clock output.
SCOR High when either subcode sync S0 or S1 is detected.
GTOP High when the sync protection window is open.
RFCK Read frame clock output.
XRAOF Low when the built-in 16K RAM exceeds the ±4 frame jitter margin.
L0 to L7, Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak
R0 to R7 data. L0 and R0 are LSB.
C1F1
0
1
1
C1F2
0
0
1
C1 correction status
No Error
Single Error Correction
Irretrievable Error
C2F1
0
1
1
C2F2
0
0
1
C2 correction status
No Error
Single Error Correction
Irretrievable Error
Command bit
CPUSR = 1
CPUSR = 0
XLON pin is high.
XLON pin is low.
Processing
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