CXD3068Q Datasheet, PDF (88/134 Pages) Sony Corporation – CD Digital Signal Processor with Built-in Digital Servo

CXD3068Q
§5-2. Digital Servo Block Master Clock (MCK)
The clock with the 2/3 frequency of the crystal is supplied to the digital servo block.
XT4D and XT2D are $3F commands, and XT1D is $3E command. (Default = 0)
The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.
Mode
1
2
3
4
5
6
7
XTAI
384Fs
384Fs
384Fs
768Fs
768Fs
768Fs
768Fs
FSTO
256Fs
256Fs
256Fs
512Fs
512Fs
512Fs
512Fs
XTSL
∗
∗
0
∗
∗
∗
1
XT4D
∗
∗
0
∗
∗
1
0
XT2D
∗
1
0
∗
1
0
0
XT1D
1
0
0
1
0
0
0
Table 5-1
Frequency division ratio MCK
1
256Fs
1/2
128Fs
1/2
128Fs
1
512Fs
1/2
256Fs
1/4
128Fs
1/4
128Fs
Fs = 44.1kHz, ∗: Don’t care
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