CXD3068Q Datasheet, PDF (48/134 Pages) Sony Corporation – CD Digital Signal Processor with Built-in Digital Servo

CXD3068Q
The setting in variable pitch mode is as shown below.
Command bit
Processing
VPCTL1 to 0, VP7 to 0 The pitch of variable pitch mode is set.
The setting of the pitch can be expressed with the equation below.
P=
–n
10
[%]
P: Setting value of pitch
n: Setting value for VPCTL1, VPCTL0 and VP7 to VP0 (two's complementary,
VPCTL1 is sign bit)
Command bit
VPCTL1 VPCTL0 VP7 to 0
00 (H)
1
0
:
FF (H)
00 (H)
1
1
:
FF (H)
00 (H)
0
0
:
FF (H)
00 (H)
0
1
:
FF (H)
Setting value of pitch [%]
+51.2
:
+25.7
+25.6
:
+0.1
0.0
:
–25.5
–25.6
:
–48.7
Example of command
setting
$D60080
:
$D6FF80
$D600C0
:
$D6FFC0
$D60000
:
$D6FF00
$D60040
:
$D6E740
The setting range of the pitch is –48.7 to +51.2%.
The pitch setting for + side should be within the playback speed of the recommended operating conditions.
The following is the example of the command in variable pitch mode.
$EX001 (Sets to CLV-N: INV VPCO = 1)
$AE4XX (Sets to use variable pitch mode)
$ACXXXXX (Variable pitch mode is turned on. The VCO2 is the reference to the internal clock.)
WAIT
(Wait time for VCO2 pull-in: until VCTL is stabilized)
$D60A00 (The pitch is set to –1.0%)
$D60000 (The pitch is set to 0.0%)
$AE4XX (Variable pitch mode is turned off. The crystal is the reference to the internal clock.)
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