CXD3068Q Datasheet, PDF (68/134 Pages) Sony Corporation – CD Digital Signal Processor with Built-in Digital Servo

CXD3068Q
[4] Description of other functions
§ 4-1. Channel Clock Regeneration by Digital PLL Circuit
• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T.
In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that
is the channel clock, is necessary.
In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the spindle
rotation alters the width of the EFM signal pulses.
The block diagram of this PLL is shown in Fig. 4-1.
The CXD3068Q has a built-in three-stage PLL.
• The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when
not using the internal VCO2, external LPF and VCO are necessary.
The output of this first-stage PLL is used as a reference for all clocks within the LSI.
• The second-stage PLL regenerates the high-frequency clock needed by the third-stage digital PLL.
• The third-stage PLL is a digital PLL that regenerates the actual channel clock.
• The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the
secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency
components such as 3T and 4T may contain deviations. In such cases, turning the secondary loop off yields
better playability. However, in this case the capture range becomes ±50kHz.
• A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition
to the conventional secondary loop.
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