CXK77P36E160GB Datasheet, PDF (5/25 Pages) Sony Corporation – 16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

SONY®
•Clock Truth Table
CXK77P36E160GB / CXK77P18E160GB
K
ZZ
SS
(t_n)
SW SBWx
(t_n)
(t_n)
Operation
X
H
X
X
X Sleep (Power Down) Mode
L→H L
H
X
L→H L
L
H
L→H L
L
L
L→H L
L
L
L→H L
L
L
X Deselect
X Read
L Write All Bytes
X Write Bytes With SBWx = L
H Abort Write
Preliminary
DQ
(t_n)
Hi - Z
Hi - Z
Q(t_n)
Hi - Z
Hi - Z
Hi - Z
DQ
(t_n+1)
Hi - Z
X
X
D(t_n)
D(t_n)
X
•Dynamic M2 Mode Pin State Changes
Although M2 is defined as a static input (that is, it must be tied “high” or “low” at power-up), in some instance (such as
during device testing) it may be desirable to change its state dynamically (that is, without first powering off the SRAM)
while preserving the contents of the memory array. If so, the following criteria must be met:
1. At least two (2) consecutive deselect operations must be initiated prior to changing the state of M2, to ensure that the
most recent read or write operation completes successfully.
2. At least thirty-two (32) consecutive deselect operations must be initiated after changing the state of M2 before any read
or write operations can be initiated, to allow the SRAM sufficient time to recognize the change in state.
•Sleep (Power Down) Mode
Sleep (power down) mode is provided through the asynchronous input signal ZZ. When ZZ is asserted (high), the output
drivers will go to a Hi-Z state, and the SRAM will begin to draw standby current. Contents of the memory array will be
preserved. An enable time (t_ZZE) must be met before the SRAM is guaranteed to be in sleep mode, and a recovery time
(t_ZZR) must be met before the SRAM can resume normal operation.
•Programmable Impedance Output Drivers
These devices have programmable impedance output drivers. The output impedance is controlled by an external resistor,
RQ, connected between the SRAM’s ZQ pin and V_SS, and is equal to one-fifth the value of this resistor, nominally. See
the DC Electrical Characteristics section for further information.
The output impedance is updated whenever the output drivers are in a Hi-Z state. Consequently, impedance updates will
occur during write and deselect operations. At power up, 8192 clock cycles followed by an impedance update via one of
the three methods described above are required to ensure that the output impedance has reached the desired value. After
power up, periodic impedance updates via write or deselect operations are also required to ensure that the output imped-
ance remains within specified tolerances.
•Power-Up Sequence
For reliability purposes, Sony recommends that power supplies power up in the following sequence: V_SS, V_DD, V_DDQ,
V_REF, and Inputs. V_DDQ should never exceed V_DD. If this power supply sequence cannot be met, a large bypass diode
may be required between V_DD and V_DDQ. Please contact Sony Memory Application Department for further information.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
5 / 25
March 2, 2001