CXK77P36E160GB Datasheet, PDF (18/25 Pages) Sony Corporation – 16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

SONY®
CXK77P36E160GB / CXK77P18E160GB
Preliminary
Bypass Register (1 bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded
with a logic “0” when the BYPASS instruction has been loaded in the the Instruction Register and the TAP Controller is
in the “Capture-DR” state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the
Instruction Register and the TAP Controller is in the “Shift-DR” state.
Boundary Scan Register (70 bits for x36, 51 bits for x18)
The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the
TAP pins) plus a number of place holder locations reserved for density and/or functional upgrades. The Boundary Scan
Register is loaded with the contents of the SRAM’s I/O ring when the SAMPLE or SAMPLE-Z instruction has been load-
ed into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO
when the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in
the “Shift-DR” state.
The Boundary Scan Register contains the following bits:
512K x 36
1M x 18
DQ
36 DQ
18
SA
19 SA
20
K, K
2 K, K
2
SS, SW, SBWx
6 SS, SW, SBWx
4
G, ZZ
2 G, ZZ
2
M1, M2
2 M1, M2
2
ZQ
1 ZQ
1
Place Holder
2 Place Holder
2
For deterministic results, all signals composing the SRAM’s I/O ring must meet setup and hold times with respect to TCK
(same as TDI and TMS) when sampled.
K/K are connected to a differential input receiver that generates a single-ended input clock signal to the device. Therefore,
in order to capture specific values for these signals in the Boundary Scan Register, these signals must be at opposite logic
levels when sampled.
Place Holders are required for some NC pins to allow for future density and/or functional upgrades. They are connected
to V_SS internally, regardless of pin connection externally.
The Boundary Scan Order Assignment table that follows depicts the order in which the bits from the table above are ar-
ranged in the Boundary Scan Register. In the notation, Bit 1 is the LSB bit of the register. When the Boundary Scan Reg-
ister is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
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March 2, 2001