CXK77P36E160GB Datasheet, PDF (4/25 Pages) Sony Corporation – 16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

SONY®
CXK77P36E160GB / CXK77P18E160GB
Preliminary
Pin Description
Symbol
Type Description
SA
DQa, DQb
DQc, DQd
Input
I/O
K, K
Input
SS
Input
SW
Input
SBWa, SBWb, Input
SBWc, SBWd
G
Input
ZZ
Input
Synchronous Address Inputs - Registered on the rising edge of K.
Synchronous Data Inputs / Outputs - Registered on the rising edge of K during write operations.
Driven from the falling edge of K during read operations.
DQa - indicates Data Byte a
DQb - indicates Data Byte b
DQc - indicates Data Byte c
DQd - indicates Data Byte d
Differential Input Clocks
Synchronous Select Input - Registered on the rising edge of K.
SS = 0 specifies a write operation when SW = 0
specifies a read operation when SW = 1
SS = 1 specifies a deselect operation
Synchronous Global Write Enable Input - Registered on the rising edge of K.
SW = 0 specifies a write operation when SS = 0
SW = 1 specifies a read operation when SS = 0
Synchronous Byte Write Enable Inputs - Registered on the rising edge of K.
SBWa = 0 specifies write Data Byte a when SS = 0 and SW = 0
SBWb = 0 specifies write Data Byte b when SS = 0 and SW = 0
SBWc = 0 specifies write Data Byte c when SS = 0 and SW = 0
SBWd = 0 specifies write Data Byte d when SS = 0 and SW = 0
Asynchronous Output Enable Input - Not supported. This control pin must be tied “low”.
Asynchronous Sleep Mode Input - Asserted (high) forces the SRAM into low-power mode.
M1
M2
ZQ
V_DD
V_DDQ
V_REF
V_SS
TCK
TMS
TDI
TDO
RSVD
Input
Input
Input
Input
Input
Input
Output
Read Operation Protocol Select 1 - This mode pin must be tied “high” to select Register - Latch
read operations.
Read Operation Protocol Select 2 - This mode pin must be tied “high” or “low”.
M2 = 0 selects Error-Correcting 8Mb R-L functionality
M2 = 1 selects conventional 16Mb R-L functionality
Output Impedance Control Resistor Input
3.3V Core Power Supply - Core supply voltage.
Output Power Supply - Output buffer supply voltage.
Input Reference Voltage - Input buffer threshold voltage.
Ground
JTAG Clock
JTAG Mode Select
JTAG Data In
JTAG Data Out
Reserved - This pin is used for Sony test purposes only. It must be left unconnected.
NC
No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these
pins. They can be left unconnected or tied directly to V_DD, V_DDQ, or V_SS.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
4 / 25
March 2, 2001