CXD2598Q Datasheet, PDF (144/147 Pages) Sony Corporation – CD Digital Signal Processor with Built-in Digital Servo and DAC

CXD2598Q
Anti Shock fs = 88.2kHz
TRK
In Reg
2 ^–1
M08
K12
Z ^–1
M09
Z ^–1
K31 K16
M0A
K35
Z ^–1
K33
2 ^–7
K34
Comp
Anti Shock
Reg
AVRG fs = 88.2kHz
Note) Set the MSB bit of the K34 coefficient to 0.
The comparator level is 1/16 the maximum amplitude of the comparator input.
VC, TE, FE,
RFDC
2 ^–1
2 ^–7
M08
Z ^–1
AVRG Reg
TRK Hold fs = 345Hz
TRK SERVO FILTER
Second-stage output
M0D
K46
THID
2 ^–1
SLD
K40
In Reg
THSK (only when TGUP2 is used)
M18
Z ^–1
M19
K45
Z ^–1
K41
2 ^–7
K42
K43
2 ^–7
K44
TRK
Hold Reg
FCS Hold fs = 345Hz
Note) Set the MSB bit of the K42 and K44 coefficients to 0.
FCS SERVO FILTER
First-stage output
M04
DFIS
($3E)
M05
FCS SERVO FILTER
Second-stage output
M1F _{K2B when using the}
K2B
FSC Gain Down filter
K0F
M1E
M10
K48
Z ^–1
K49
2 ^–7
K4A
M11
Z ^–1
K4B
2 ^–7
K4C
K4D
M12
FCS
Hold Reg 2
Note) Set the MSB bit of the K4A and K4C coefficients to 0.
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