LAN9217 Datasheet, PDF (94/134 Pages) SMSC Corporation – 16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
BITS
DESCRIPTION
0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9217
will assert back pressure, or transmit a pause frame when the AFC level is
reached and any frame is received. Setting this bit enables full-duplex flow
control when the LAN9217 is operating in full-duplex mode.
When this mode is enabled during half-duplex operation, the Flow Controller
does not decode the MAC address and will send a pause frame upon
receipt of a valid preamble (i.e., immediately at the beginning of the next
frame after the RX data FIFO level is reached).
When this mode is enabled during full-duplex operation, the Flow Controller
will immediately instruct the MAC to send a pause frame when the RX data
FIFO level is reached. The MAC will queue the pause frame transmission
for the next available window.
Setting this bit overrides bits [3:1] of this register.
TYPE
R/W
DEFAULT
0
[19:16]
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
Table 5.5 Backpressure Duration Bit Mapping
BACKPRESSURE DURATION
100Mbs Mode
5uS
10uS
15uS
25uS
50uS
100uS
150uS
200uS
250uS
300uS
350uS
400uS
450uS
500uS
550uS
600uS
10Mbs Mode
7.2uS
12.2uS
17.2uS
27.2uS
52.2uS
102.2uS
152.2uS
202.2uS
252.2uS
302.2uS
352.2uS
402.2uS
452.2uS
502.2uS
552.2uS
602.2uS
Revision 1.5 (07-18-06)
94
DATASHEET
SMSC LAN9217