LAN9217 Datasheet, PDF (58/134 Pages) SMSC Corporation – 16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
Host Read
Order
1st
2nd
Last
31
0
Optional offset DWORD0
.
.
Optional offset DWORDn
ofs + First Data DWORD
.
.
.
.
Last Data DWORD
Optional Pad DWORD0
.
.
Optional Pad DWORDn
Figure 3.18 RX Packet Format
3.15.3 The LAN9217 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits
wide. Figure 3.18 describes the host read ordering for pairs of atomic 16-bit transactions.RX Status Format
BITS
31
30
29:16
15
14
13
12
DESCRIPTION
Reserved. This bit is reserved. Reads 0.
Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing
filtering.
Packet Length. The size, in bytes, of the corresponding received frame.
Error Status (ES). When set this bit indicates that the MIL has reported an error. This bit is the
Internal logical “or” of bits 11,7,6 and 1.
Reserved. These bits are reserved. Reads 0.
Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address.
Length Error (LE). When set, this bit indicates that the actual length does not match with the
length/type field of the received frame.
Revision 1.5 (07-18-06)
58
DATASHEET
SMSC LAN9217