LAN83C185_03 Datasheet, PDF (9/65 Pages) SMSC Corporation – High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Chapter 1 General Description
1.1
The SMSC LAN83C185 is a low-power, highly integrated analog interface IC for high-performance
embedded Ethernet applications. The LAN83C185 requires only a single +3.3V supply.
The LAN83C185 consists of an encoder/decoder, scrambler/descrambler, transmitter with wave-
shaping and output driver, twisted-pair receiver with on-chip adaptive equalizer and baseline wander
(BLW) correction, clock and data recovery, and Media Independent Interface (MII).
The LAN83C185 is fully compliant with IEEE 802.3/ 802.3u standards and supports both 802.3u-
compliant and vendor-specific register functions. It contains a full-duplex 10-BASET/100BASE-TX
transceiver and supports 10-Mbps (10BASE-T) operation on Category 3 and Category 5 unshielded
twisted-pair cable, and 100-Mbps (100BASE-TX) operation on Category 5 unshielded twisted-pair
cable.
Architectural Overview
MODE0
MODE1
MODE2
nRESET
TXD[0..3]
TX_EN
TX_ER
TX_CLK
RXD[0..3]
RX_DV
RX_ER
RX_CLK
CRS
COL
MDC
MDIO
MODE Control
1.8V
Regulator
Auto-
Negotiation
Transmit Section
10M Tx
Logic
10M
Transmitter
Management
SMI
Control
100M Tx
Logic
100M
Transmitter
Receive Section
100M Rx
Logic
DSP System:
Clock
Data Recovery
Equalizer
Analog-to-
Digital
PLL
Interrupt
Generator
10M Rx
Logic
100M PLL
Squelch &
Filters
PHY
Address
Latches
LED Circuitry
10M PLL
Central
Bias
GPO Circuitry
TXP / TXN
XTAL1
XTAL2
nINT
RXP / RXN
PHYAD[0..4]
SPEED100
LINKON
ACTIVITY
FDUPLEX
GPO0
GPO1
GPO2
Figure 1.1 LAN83C185 Architectural Overview
SMSC LAN83C185
1
DATASHEET
Rev. 0.6 (12-12-03)