LAN83C185_03 Datasheet, PDF (51/65 Pages) SMSC Corporation – High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
5.5.1.2
General Characteristics
ITEM
Full Scale Input voltage
Input Common Mode
SPEC
3.0 Differential (peak-to-peak)
1.6-2.0
UNITS
REMARK
V
V
Gain dependent.
5.5.2
5.5.2.1
5.5.3
5.5.3.1
5.5.4
5.5.5
5.5.6
100M PLL
Three main functions are included in the 100M PLL: a clock multiplier to generate a 125MHz clock, a
phase interpolator to synchronize the receive clock to the receive data, and a transmit wave-shaping
delay reference.
Functional Description
The clock multiplier generates a multiple phase 125MHz from a 25MHz reference frequency.
The phase interpolator uses a multiplexer to select the phase used as the receive clock, RX_CLK. The
multiplexer is controlled by signals generated in the DSP Timing unit. The Timing unit estimates the
frequency drift of the received data clock and, by incrementing, decrementing or maintaining the
selected phase, it generates a clock that is synchronized to the received data stream.
The 100M PLL also generates a fixed phase 125MHz clock, slaved to the VCO, that is used by the
digital filter for accurate wave-shaping of the transmit output. It is also used as the transmitter clock of
the PHY, TX_CLK. (This clock must be jitter-free thus cannot be the receive clock).
MT_100
This block generates the differential outputs driven onto TXP/TXN in 100Base-TX mode.
Functional Description
This block is a wave-shaped 100BASE-TX transmitter, with high impedance current outputs. The three
level differential output (MLT-3) is shaped by differential current switches whose outputs are connected
together. The low pass filtering (wave-shaping) of the current output is done by progressive switching
of small current sources. The timing reference for the wave-shaping is the 125MHz fixed clock from
the 100M PLL. The transmitter is designed to operate with a 1:1 transformer.
10M Squelch
The squelch circuit consists of squelch comparators and data comparators, which operate according
to the 802.3 standard in Section 14.3.1.3.2.
10BT Filter
The 10BASE-T Low Pass Filter is the front end of 10BASE-T signal path. It is designed to reject the
high frequency noise from entering the squelch and data recovery blocks.
10M PLL - Data Recovery Clock
The data recovery Phase Locked Loop (PLL) is used for data recovery for the 10BASE-T mode of
operation. The data recovery PLL is used to synchronize the phase of the 10BASE-T data and the
20MHz VCO.
SMSC LAN83C185
43
DATASHEET
Rev. 0.6 (12-12-03)