LAN83C185_03 Datasheet, PDF (37/65 Pages) SMSC Corporation – High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
5.1
SMI Register Mapping
The following registers are supported (register numbers are in decimal):
Table 5.33 SMI Register Mapping
REGISTER #
0
1
2
3
4
5
6
16
17
18
20
21
22
23
27
28
29
30
31
DESCRIPTION
Basic Control Register
Basic Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Silicon Revision Register
Mode Control/Status Register
Special Modes
TSTCNTL – Testability/Configuration Control
TSTREAD1 – Testability data Read for LSB
TSTREAD2 – Testability data Read for MSB
TSTWRITE – Testability/Configuration data Write
Control / Status Indication Register
Special internal testability controls
Interrupt Source Register
Interrupt Mask Register
PHY Special Control/Status Register
GROUP
Basic
Basic
Extended
Extended
Extended
Extended
Extended
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
5.2
SMI Register Format
The mode key is as follows:
■ RW = read/write,
■ SC = self clearing,
■ WO = write only,
■ RO = read only,
■ LH = latch high, clear on read of register,
■ LL = latch low, clear on read of register,
■ NASR = Not Affected by Software Reset
SMSC LAN83C185
29
DATASHEET
Rev. 0.6 (12-12-03)