COM20020I Datasheet, PDF (59/72 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
A0-A2
VALID
t1
t2
nCS
DIR
nDS
D0-D7
t3
t5
t8
t4
t6
t10
VALID DATA
t7
t11
t9 ^{Note 2}
CASE 1: RBUSTMG bit = 0
Parameter
t1 Address Setup to nDS Active
t2 Address Hold from nDS Inactive
t3 nCS Setup to nDS Active
t4 nCS Hold from nDS Inactive
t5 DIR Setup to nDS Active
t6 Cycle Time (nDS Low to Next Time Low)
t7 DIR Hold from nDS Inactive
t8 nDS Low to Valid Data
t9 nDS High to Data High Impedence
t10 nDS Low Width
t11 nDS High Width
min
15
10
5**
0
10
4TARB*
10
0
60
20
max
40**
20
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
** nCS may become active after control becomes active, but the access time (t8) will
now be 45nS measured from the leading edge of nCS.
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 2: _{Read cycle for Address Pointer Low/High Registers occurring after an access}
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
SMSC COM20020I Rev D
Page 59
DATASHEET
Revision 12-05-06