COM20020I Datasheet, PDF (53/72 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Chapter 8 Timing Diagrams
AD0-AD2,
D3-D7
nCS
ALE
nDS
DIR
VALID
t1
t2,
t4
t3
t11
t6
t5
t9
VALID DATA
t12
t13
t8
t7
t14
Note 2
t10
MUST BE: RBUSTMG bit = 0
Parameter
min
t1 Address Setup to ALE Low
t2 Address Hold from ALE Low
t3 nCS Setup to ALE Low
t4 nCS Hold from ALE Low
t5 ALE Low to nDS Low
t6 nDS Low to Valid Data
t7 nDS High to Data High Impedance
t8 Cycle Time (nDS Low to Next Time Low)
t9 DIR Setup to nDS Active
t10 DIR Hold from nDS Inactive
t11 ALE High Width
t12 ALE Low Width
t13 nDS Low Width
t14 nDS High Width
20
10
10
10
15
0
4TARB*
10
10
20
20
60
20
max units
nS
nS
nS
nS
nS
40
nS
20
nS
nS
nS
nS
nS
nS
nS
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 2: _{Read cycle for Address Pointer Low/High Registers occurring after an access}
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Figure 8.1 – Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
SMSC COM20020I Rev D
Page 53
DATASHEET
Revision 12-05-06