COM20019I_06 Datasheet, PDF (56/65 Pages) SMSC Corporation – Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM

Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM
A0-A2
nCS
nRD
nWR
D0-D7
t1
t3
Note 3
t10
VALID
t2
t4
t8
t9
t5
t6
VALID DATA
Note 2
t5**
t7
Parameter
t1 Address Setup to nWR Active
t2 Address Hold from nWR Inactive
t3 nCS Setup to WR Active
t4 nCS Hold from nWR Inactive
t5 Cycle Time (nWR to Next )**
t6 Valid Data Setup to nWR High
t7 Data Hold from nWR High
t8 nWR Low Width
t9 nWR High Width
t10 nRD to nWR Low
min
15
10
5
0
4TARB*
30***
10
20
20
20
max
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
Note 1: The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
**Note ^2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: _{Write cycle for Address Pointer Low Register occurring after a read from Data}
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
Figure 8.9 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE
Rev. 03-07-06
Page 56
DATASHEET
SMSC COM20019I