COM20019I_06 Datasheet, PDF (27/65 Pages) SMSC Corporation – Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM

Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM
6.2.13 Setup 2 Register
The Setup 2 Register is new to the COM20019I. It is an 8-bit read/write register accessed when the Sub
Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register). This
register contains bits for various functions. The CKUP1,0 bits select the clock to be generated from the 20
MHz crystal. The RBUSTMG bit is used to Disable/Enable Fast Read function for High Speed CPU bus
support. The EF bit is used to enable the new timing for certain functions in the COM20019I (if EF = 0, the
timing is the same as in the COM20020 Rev. B). See Appendix “A”. The NOSYNC bit is used to enable
the NOSYNC function during initialization. If this bit is reset, the line has to be idle for the RAM
initialization sequence to be written. If set, the line does not have to be idle for the initialization sequence
to be written. See Appendix “A”.
The RCNTM[1,0] bits are used to set the time-out period of the recon timer. Programming this timer for
shorter time periods has the benefit of shortened network reconfiguration periods. The time periods shown
in the table on the following page are limited by a maximum number of nodes in the network. These time-
out period values are for 312.5 Kbps. For other data rates, scale the time-out period time values
accordingly; the maximum node count remains the same.
Note 6.1
RCNTM1
0
0
1
1
RCNTM0
0
1
0
1
TIME-OUT PERIOD
6.72 S
1.68 S
840 mS
420 mS*
MAX NODE
COUNT
Up to 255 nodes
Up to 64 nodes
Up to 32 nodes
Up to 16 nodes
(See Note 6.1)
The node ID value 255 must exist in the network for the 420 mS time-out to be valid.
Table 6.3 - Status Register
BIT BIT NAME SYMBOL
DESCRIPTION
7 Receiver
Inhibited
RI
This bit, if high, indicates that the receiver is not enabled because
either an "Enable Receive to Page fnn" command was never
issued, or a packet has been deposited into the RAM buffer page
fnn as specified by the last "Enable Receive to Page fnn"
command. No messages will be received until this command is
issued, and once the message has been received, the RI bit is
set, thereby inhibiting the receiver. The RI bit is cleared by
issuing an "Enable Receive to Page fnn" command. This bit,
when set, will cause an interrupt if the corresponding bit of the
Interrupt Mask Register (IMR) is also set. When this bit is set and
another station attempts to send a packet to this station, this
station will send a NAK.
6,5 (Reserved)
These bits are undefined.
4 Power On Reset POR
This bit, if high, indicates that the COM20019I has been reset by
either a software reset, a hardware reset, or writing 00H to the
Node ID Register. The POR bit is cleared by the "Clear Flags"
command.
3 Test
TEST
This bit is intended for test and diagnostic purposes. It is a logic
"0" under normal operating conditions.
SMSC COM20019I
Page 27
DATASHEET
Rev. 03-07-06