LPC47M112-MC Datasheet, PDF (29/193 Pages) SMSC Corporation – ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE

BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data
rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.
BIT 2 through 4 PRECOMPENSATION SELECT
These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7
shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track
number to start precompensation. this starting track number can be changed by the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and
data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset
or access to the Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.
Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the
runtime register block. Separator circuits will be turned off. The controller will come out of manual low power.
Table 7 - Precompensation Delays
PRECOMP
432
111
001
010
011
100
101
110
000
PRECOMPENSATION DELAY (nsec)
<2Mbps
2Mbps
0.00
0
41.67
20.8
83.34
41.7
125.00
62.5
166.67
83.3
208.33
104.2
250.00
125
Default
Default
Default: See Table 10
Table 8 - Data Rates
DRIVE RATE
DRT1
0
0
0
0
0
0
0
0
1
1
1
1
DRT0
0
0
0
0
1
1
1
1
0
0
0
0
DATA RATE
SEL1
1
0
0
1
1
0
0
1
1
0
0
1
SEL0
1
0
1
0
1
0
1
0
1
0
1
0
DATA RATE
MFM FM
1Meg
---
500
250
300
150
250
125
1Meg
---
500
250
500
250
250
125
1Meg
---
500
250
2Meg
---
250
125
DENSEL
1
1
0
0
1
1
0
0
1
1
0
0
DRATE(1)
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
SMSC DS – LPC47M112
Page 29
Rev. 01/09/2001