LPC47M112-MC Datasheet, PDF (161/193 Pages) SMSC Corporation – ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE

NAME
Default = 0x03
on VCC POR,
VTR POR and
HARD RESET
REG INDEX
DEFINITION
0= blank during transmit/receive
1= blank during transmit/receive + 100usec
...
Note 1: The TXD2_MODE bit is a VTR powered bit that is reset on VTR POR only.
STATE
Table 69 - KYBD, Logical Device 7 [Logical Device Number = 0x07]
NAME
KRST_GA20
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
REG INDEX
0xF0
R/W
0xF1 - 0xFF
DEFINITION
KRESET and GateA20 Select
Bit[7] Polarity Select for P12
= 0 P12 active low (default)
= 1 P12 active high
Bit[6] M_ISO. Enables/disables isolation of mouse
signals into 8042. Does not affect MDAT signal to mouse
wakeup (PME) logic.
1=block mouse clock and data signals into 8042
0= do not block mouse clock and data signals into 8042
Bit[5] K_ISO. Enables/disables isolation of keyboard
signals into 8042. Does not affect KDAT signal to
keyboard wakeup (PME) logic.
1=block keyboard clock and data signals into 8042
0= do not block keyboard clock and data signals into
8042
Bit[4] MLATCH
= 0 MINT is the 8042 MINT ANDed with Latched MINT
(default)
= 1 MINT is the latched 8042 MINT
Bit[3] KLATCH
= 0 KINT is the 8042 KINT ANDed with Latched KINT
(default)
= 1 KINT is the latched 8042 KINT
Bit[2] Port 92 Select
= 0 Port 92 Disabled
= 1 Port 92 Enabled
Bit[1] Reserved
Bit[0] Reserved
Reserved - read as ‘0’
STATE
NAME
CLOCKI32
Default = 0x00
on VTR POR
Table 70 - PME, Logical Device A
REG INDEX
0xF0
(R/W)
DEFINITION
Bit[0] (CLK32_PRSN)
0=32kHz clock is connected to the CLKI32
pin (default)
1=32kHz clock is not connected to the CLKI32
pin (pin is grounded)
Bit[1] SPEKEY_EN. This bit is used to turn the logic
for the “wake on specific key” feature on and off. It will
disable the 32kHz clock input to the logic when turned
off. The logic will draw no power when disabled.
0= “Wake on specific key” logic is
on (default)
1= “Wake on specific key” logic is off
Bits[7:2] are reserved
STATE
C
NAME
MPU-401 Primary
Base I/O Address
High Byte
Table 71 – MPU-401 [Logical Device Number = 0x0B]
REG INDEX
0x60 R/W Bit[0] A8
Bit[1] A9
Bit[2] A10
DEFINITION
STATE
C
SMSC DS – LPC47M112
Page 161
Rev. 01/09/2001