37C957FR Datasheet, PDF (23/328 Pages) SMSC Corporation – ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS

FDC37C957FR OPERATING REGISTERS
The address map, shown below in Table 3, shows the set of operating registers and addresses for
each of the logical blocks of the FDC37C957FR Ultra I/O controller. The base addresses of the
FDC, Parallel, Serial 1 and Serial 2 ports can be moved via the configuration registers.
HOST PROCESSOR INTERFACE
The host processor communicates with the FDC37C957FR through a series of read/write registers.
The range of base I/O port addresses for these registers is shown in Table 3. Register access is
accomplished through programmed I/O or DMA transfers. All registers are 8 bits. Most of the
registers support zero wait-state access (NOWS). All host interface output buffers are capable of
sinking a minimum of 12 mA.
Logical
Device
Number
0x00
Table 3- FDC37C957FR OPERATING REGISTER ADDRESSES
Logical
Base I/O
Fixed
NOWS
ISA Cycle
Device
Range
(note3)
Base Offsets
Type
FDC
[0x100:0x0FF8]
ON 8 BYTE
BOUNDARIES
+0 : SRA
+53214 : FTDSMISROSFRBOR/DSR
+7:DIR/CCR
NOWS
0x03
Parallel
Port
[0x100:0x0FFC]
ON 4 BYTE
BOUNDARIES
(EPP Not supported)
or
[0x100:0x0FF8]
ON 8 BYTE
BOUNDARIES
(all modes
supported,
EPP is only available
when the base
address is on an 8-
byte boundary)
+0 : Data | ecpAfifo
+4120:0SChtoa:ntutcrsofitflfoifo| e| cpnDfgfAifo |
+401h : cnfgB
+402h : ecr
17