37C957FR Datasheet, PDF (146/328 Pages) SMSC Corporation – ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS

System Reset Sequence
System is running
[VCC2 ON, VCC1 ON]
8051 executing keyboard firmware.
Somehow a reset event is
conveyed to the 8051.
cmd from host, and/or directly
from a GPI/O type pin transition?
8051asserts iRESET_OUT
RESET_OUT pin
8051 programs the
Stop Clock Counter
STP_CNT[3:0] <- X
8051 releases the system
reset (iRESET_OUT
register bit is reset)
(Note 1)
8051goes into idle mode
N stop-clock cnt ^Y
=0?
Note1: IRESET_OUT being reset to 0
(Togglingfrom1to0 )
1) sets 8051STP_CLK[0]=1
2) sets HMEM[7:0]=03h.
and
3) causes the StopClock
Counter to start counting
down.
Note2: In order to leave idle mode the
8051 must receive an interrupt,
typically a software timer interrupt
will be used.
RESET_OUT de-asserted
RESET_OUT = low &
8051STP_CLK = 1 cause
8051 clock to stop.
RESET_OUT pin
Host now owns Flash
Interface,
shadows Flash to RAM
Host resets
8051STP_CLK bit
N
8051 Timer
IRQ ?
Y
(Note)
8051 wakes up from idle
mode and starts executing
from where it left off
RESET SEQUENCE
FIGURE 4 - TYPICAL SYSTEM RESET SEQUENCE
140