LPC47N267 Datasheet, PDF (175/180 Pages) SMSC Corporation – 100 Pin LPC Notebook I/O with X-Bus Interface

Representative LPC I/O Cycle to X-Bus Cycle Timing
X-Bus Read Cycle: LPC I/O Read Cycle – Data from X-Bus Device to Host
PCI_CLK
LFRAME#
LAD[3:0]# ^StartC+D
Address
TAR
Ax, nXCSx
nXRD
Data
Sync=0110
Sync
0000
Data
TAR
Valid
FIGURE 34 – X-BUS AND LPC I/O READ CYLE
Note: Minimum read pulse width is shown.
SMSC DS – LPC47N267
Page 175
Rev. 10/23/2000