LPC47N267 Datasheet, PDF (122/180 Pages) SMSC Corporation – 100 Pin LPC Notebook I/O with X-Bus Interface

20.4.11 CR0A
CR0A can only be accessed in the configuration state and after the CSR has been initialized to 0AH. CR0A defines
the FIFO threshold for the ECP mode parallel port. Bits [5:4] are Reserved. Reserved Bits cannot be written and
return 0 when read. Bits [7:6] are the IR OUTPUT MUX bits and are reset to the default state by a POR and a
hardware reset.
BIT NO.
0
1
2
3
TYPE: R/W
BIT NAME
THR0
THR1
THR2
THR3
Table 66 – CR0A
ECP FIFO THRESHOLD/IR MUX
DEFAULT: 0x00 on VCC POR;
Bits[7:5] = 00 on HARD RESET
DESCRIPTION
ECP FIFO Threshold 0.
ECP FIFO Threshold 1.
ECP FIFO Threshold 2.
ECP FIFO Threshold 3.
4
Reserved
Read Only. A read returns 0.
5
TXD2 Tristate 0 = No effect on TXD2
1 = When serial port 2 is deactivated (power down bit=0) the TXD2
pin is tristate. When the device is activated, TXD2 will depend on
CR0A bits [7:6].
6,7
IR Output Mux These bits are used to select IR Output Mux Mode.
BIT7
BIT6
MUX MODE
0
0
Active device to COM port (Default).
That is, depending on the mode of
Serial Port 2, use Pins 92, 94-100
for COM signals or use RXD2 and
TXD2 (pins 95 and 96) for IR.
When Serial Port 2 is inactive
(Power Down bit = 0), then TXD2
pin is low. The IRTX2 pin is low.
0
1
Active device to IR port. That is,
use IRRX2, IRTX2 (pins 61, 62).
When Serial Port 2 is inactive
(Power Down bit = 0), then IRTX2
pin is low. The TXD2 pin is low.
1
0
Reserved.
1
1
Outputs Inactive: TXD2 and IRTX2
are High-Z, regardless of mode of
UART2 and state of UART2
powerdown bit.
20.4.12 CR0B
CR0B can only be accessed in the configuration state and after the CSR has been initialized to 0BH. CR0B indicates
the Drive Rate table (Table 68) used for each drive. Refer to section CR1F for the Drive Type register.
BIT NO.
0
1
2
TYPE: R/W
BIT NAME
DTR0
DTR1
DTR0
Table 67 – CR0B
DRIVE RATE
DEFAULT: 0X00 ON VCC POR
DESCRIPTION
Floppy Disk Drive 0 Drive Rate Table Bit 0.
Floppy Disk Drive 0 Drive Rate Table Bit 1.
Floppy Disk Drive 1 Drive Rate Table Bit 0.
SMSC DS – LPC47N267
Page 122
Rev. 10/23/2000