47N350 Datasheet, PDF (167/346 Pages) SMSC Corporation – LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE

Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
HOST
8051
POWER
DEFAULT
Table 13.16 RSTGA20L
N/A
0x7FFF (W)
VCC1
N/A
Refer to the GATEA20 Hardware Speed-up description for information on this register. A write to this
register resets GateA20.
nIOW
Address
Data
SAEN
64&nAEN
nIO W _D LY
DD1
SD[7:0] = D1
SD[7:0] = FF ^DFF
SD[7:0] = FE ^DFE
nAEN&60
nIOW
nAEN&64
nIOW
nAEN&60
DD1
After D1
DQ
R
D
Trailing Edge Delay
Port92 Reg
Bit 1
ENAB_P92
GateA20 Logic
n IO W _ D L Y
nIOW
nIOW
To KRESET Gen
D
Q
IBF
IBF Bit
CPU_RESET
SETGA20L Reg
Any Write
0
A20
MUX
1
SD[1]
RSTGA20L Reg
Any Write
S
Fast_GateA20
DQ
R
GATEA20 Reg
W rite
d0 _bit-0
GATEA20 Reg
Read
d0
bit-0
SAEN
bit-1 of
Config Reg 0
ALT_A20
GATEA20
nIOW
24MHz
DQ
n IO W _ D L Y
DQ
VCC
Delay
D
nQ
R
Figure 13.1 GATEA20 Implementation Diagram
13.4.2 CPU_RESET Hardware Speed-Up
The ALT_CPU_RESET bit generates, under program control, the nALT_RST signal, which provides an
alternate, means to drive the LPC47N350 CPU_RESET pin which in turn is used to reset the Host CPU.
The nALT_RST signal is internally NANDed together with the nKBDRESET pulse from the KRESET
Speed up logic to provide an alternate software means of resetting the host CPU. Note: before another
nALT_RST pulse can be generated, ALT_CPU_RESET must be cleared to “0” either by a system reset
(nRESET_OUT asserted) or by a write to the Port92 register with bit 0 = “0”. A nALT_RST pulse is not
generated in the event that the ALT_CPU_RESET bit is cleared and set before the prior nALT_RESET
pulse has completed.
SMSC LPC47N350
149
DATASHEET
Revision 1.1 (01-14-03)