47N350 Datasheet, PDF (119/346 Pages) SMSC Corporation – LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE

Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
8.3.7.8
Set Main Block Access Mode
The Set Main Block Access mode uses the CSI host interface to disconnect the flash memory array
from the DOUT bus, selects the Main Memory block in the Flash Memory Array, resets the INFO bit in
the CSI status register to ‘0’ (see Section 8.3.6.5, "Info Bit – D3"), and makes the CSI status register
available for subsequent host read cycles (Figure 8.3).
The CSI flash interface sets the Flash Memory Array interface signals to the standby mode for the
duration of the Set Main Block Access mode.
The CSI host interface and the Flash Memory Array interface remain in the Read Status (Idle) mode
until the next command is given.
8.3.7.9
Set Info Block Access Mode
The Set Info Block Access mode uses the CSI host interface to disconnect the flash memory array from
the DOUT bus, selects the Information Memory block in the Flash Memory Array, sets the INFO bit in
the CSI status register to ‘1’ (see Section 8.3.6.5, "Info Bit – D3"), and makes the CSI status register
available for subsequent host read cycles (Figure 8.3).
The CSI flash interface sets the Flash Memory Array interface signals to the standby mode for the
duration of the Set Info Block Access mode.
The CSI host interface and the Flash Memory Array interface remain in the Read Status (Idle) mode
until the next command is given.
8.3.7.10 CSI Host Interface Error Handling
Command Errors
When a write to the CSI command register has been attempted while the BUSY bit is asserted, the write
data is rejected (i.e. the data in the command register is not overwritten), the state machine asserts the
CMD ERROR bit in the CSI status register, and the command in progress continues to completion.
When a RESERVED command code is written to the CSI command register when the BUSY bit is
deasserted, the data in the command register is ignored, the state machine asserts the CMD ERROR
bit in the CSI status register, and the CSI host interface transitions to the IDLE state (not shown in
Figure 8.3).
For information regarding RESERVED command codes see Note 8.1 in Table 8.6 and Section 8.3.6.2,
"CMD Error Bit – D6". For information regarding the BUSY bit see Section 8.3.6.1, "Busy Bit – D7".
Write Protect Errors
When a byte programming or erase operation has been requested for write-protected memory, the
command is rejected, the state machine asserts the PROTECT ERROR bit in the CSI status register
and transitions to the IDLE state (not shown in Figure 8.3).
For information regarding write-protection errors see Section 8.4, "Flash Write Protect" and Section
8.3.6.3, "Protect Error Bit – D5".
Setup Errors
When a PROGRAM BYTE or ERASE PAGE command code cycle has been followed by a read bus
cycle instead of a write cycle, the command is terminated, the state machine asserts the SETUP
ERROR bit in the CSI status register and transitions to the IDLE state (not shown in Figure 8.3).
For information regarding setup errors see Section 8.3.5, "CSI Command Types" and Section 8.3.6.4,
"Setup Error Bit – D4".
SMSC LPC47N350
101
DATASHEET
Revision 1.1 (01-14-03)