37C672 Datasheet, PDF (164/173 Pages) SMSC Corporation – ENHANCED SUPER I/O CONTROLLER WITH FAST IR

Chapter 22
Enhanced Super I/O Controller with Fast IR
Datasheet
ECP Parallel Port Timing
Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using
DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to
Figure 22.2.
ECP Parallel Port Timing
The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter
cable is used then the bandwidth will increase.
Forward-Idle
When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk
(Busy) low.
Forward Data Transfer Phase
The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck
and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest.
The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward
Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel
be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk
(nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior
to the falling edge of HostClk. The peripheral then sets
PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The
peripheral then accepts the data and sets PeriphAck (Busy) low,
completing the transfer. This sequence is shown in Figure 22.2.
The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously
with HostClk (nStrobe).
Reverse-Idle Phase
The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low.
Reverse Data Transfer Phase
The interface transfers data and commands from the peripheral to the host using an interlocked HostAck
and PeriphClk.
The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte
has been accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low
when it has data to send. The data must be stable for the specified setup time prior to the falling edge of
PeriphClk. When the host is ready to accept a byte it sets HostAck (nALF) high to acknowledge the
handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets
HostAck (nALF) low, completing the transfer. This sequence is shown in Figure 22.3.
SMSC FDC37C672
Page 164
DATASHEET
Rev. 10-29-03